1. Technical Field
The present invention relates in general to digital electronic memory devices and in particular to electronic memory devices having redundant data storage. Still more particularly, the present invention relates to electronic memory devices having redundant data storage and dual-port memory access.
2. Description of the Related Art
In high speed data processing systems, cache memory is utilized to decrease the effective time to access data stored in main memory. Cache memory is a buffer that stores selected data copied from a larger and usually slower area of main memory. Cache memory allows the system processor to retrieve data faster than if the processor had to retrieve the data from the main memory. Processor throughput increases as fewer processor machine cycles are wasted waiting for data requested from slower memory. Ideally, a cache memory read or write cycle may be executed within one processor machine cycle. Hence, the processor will not have to wait while a cache memory operation executes. By including cache memory in the data processing system design, processor machine cycles previously spent waiting for data from slower main memory may now be used to perform useful operations.
Processor throughput is only increased, however, if the data requested by the processor is stored within cache memory. The use of cache memory is based upon the principle that certain data has a higher probability at any given time of being selected next by the processor than other data. If such higher probability data are stored in a cache, then average access time for the data will be decreased. Therefore, data is frequently moved into and out of cache memory in an attempt to increase the probability of a cache "hit". A cache hit occurs when the next data required by the processor is located in cache memory and the processor is able to quickly access the data.
Frequently, in an effort to efficiently manage the contents of cache memory, a memory management unit (MMU), or some other device, attempts to shuffle data into and out of cache memory while the central processing unit (CPU) is also attempting to access cache memory. One solution to the need for such simultaneous access to cache memory is to utilize a dual-port memory which allows a single memory array to be accessed simultaneously by two devices. One disadvantage of utilizing a dual-port memory is the high cost associated with a device having a relatively large chip size. Dual-port memory chips may be more than twice as large as a single-port memory chip. A large chip size may reduce manufacturing yield. Manufacturing yield is the ratio of the number of good chips produced to the total number of chips fabricated.
In addition to providing a cache memory having a cycle time as fast as the machine cycle of the main processor, another goal of data processing system design is to protect data integrity and avoid single point failures. One way to accomplish such a goal is to utilize a memory with redundant data storage. Each time data is written to a memory with redundant storage, two copies of the data are stored in two separate memory arrays. If an error is detected in the data in one array (by utilizing a parity check, for example), data from a second array is used instead. The disadvantages of utilizing redundant memory are the size and cost of the memory chip. A redundant memory chip requires two memory arrays, and therefore twice the area on a silicon chip. As discussed above, a larger chip size reduces manufacturing yields, which may increase manufacturing costs.
A conventional data processing system requiring dual-port cache memory with redundant data storage may have to utilize memory chips four times larger than a single-port memory device; dual-port capability may double the chip size and data redundancy may double the size again. Thus, it should be apparent that a need exists for a cache memory having dual-port and redundant storage capability in a configuration that occupies approximately half the space of a conventional memory with the same capability.